This application claims the priority of Korean Patent Application No. 2003-2093, filed on Jan. 13, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a field emission display (FED) with a double gate structure and a method of manufacturing thereof, and more particularly, to a field emission display (FED) in which short circuit between an emitter and a double gate can be prevented, and a method of manufacturing thereof.
2. Description of the Related Art
Displays, which are an important part of conventional information transmission media, include PC monitors and televisions (TVs). Displays are classified into cathode ray tubes (CRTs) using high-speed thermal electron emission and flat panel displays that have been recently developed at a very high speed. Flat panel displays include liquid crystal displays (LCDs), plasma display panels (PDPs), and field emission displays (FEDs).
Field emission displays (FEDs) apply a strong electric field from a gate to a field emitter disposed on a cathode layer at regular intervals, thereby emitting electrons from the field emitter, colliding the electrons with a phosphor material of an anode layer, and emitting light. In the prior art, a micro-tip formed of metal, such as molybdenum (Mo), is used as a field emitter for FEDs. However, recently, carbon nanotubes are widely being used as the field emitter for FEDs. Since FEDs using carbon nanotubes (CNTs) have the advantages of a wide range of vision, high resolution, low power, and temperature stability, FEDs has a variety of applications such as a car navigation device and a viewfinder for an electronic display. In particular, FEDs can be used as a replacement for other types of displays for PCs, personal data assistant (PDA) terminals, medical equipment, and a high definition televisions (HDTVs).
Two structures of conventional field emission displays (FEDs) are shown in FIGS. 1 and 2. Referring to FIG. 1, a conventional FED includes a substrate 10, a cathode layer 11, a first insulating layer 12, a first gate layer 13, a second insulating layer 14, and a second gate layer 15, which are sequentially stacked on the substrate 10. A cavity 17 having a predetermined diameter is formed on the first and second insulating layers 12 and 14, respectively. A first gate hole 13a and a second gate hole 15a which correspond to the cavity 17, are formed in the first and second gate layers 13 and 15, respectively. A field emitter 19 is provided on the cathode layer 11 exposed through the cavity 17. Here, a glass substrate is widely used as the substrate 10, and the cathode layer 11 is formed of indium tin oxide (ITO) which is a transparent conductive material. The field emitter 19 is formed of carbon nanotubes or a metal tip, as described above.
A conventional FED shown in FIG. 2 includes a substrate 20, a cathode layer 21, a first insulating layer 22, a first gate layer 23, a second insulating layer 24, and a second gate layer 25, which are sequentially stacked on the substrate 20. A first cavity 27 and a first gate hole 23a having the same diameter are formed in the first insulating layer 22 and the first gate layer 23, respectively. A second cavity 28 and a second gate hole 25a having a diameter greater than the diameter of the first cavity 27 are formed in the second insulating layer 24 and the second gate layer 25, respectively. Carbon nanotubes (CNTs) or a metal tip are used for a field emitter 29 in the first cavity 27.
As shown in FIGS. 1 and 2, the FEDs with a double gate structure control voltages applied to the second gate layers 15 and 25, and thus prevent divergence of electron beams emitted from the field emitters 19 and 29. As such, the electron beams are focused as beam spots having a smaller size at a desired position of an anode layer. Thus, more clear picture quality can be achieved. Also, in these aforementioned FEDs, an electrical arc which may occur between the FEDs and the anode layer, can be discharged through the second gate layers 15 and 25 closer to the anode layer. Thus, the electrical arc does not directly affect the field emitters 19 and 29 which serve to emit electron beams, the cathode layers 11 and 21, and the first gate layers 13 and 23.
In particular, the FED shown in FIG. 1 has the narrower and deeper cavity 17 and gate holes 13a and 15a, and thus has the advantage of a higher focusing characteristic of electron beams emitted from the field emitter 19. The FED shown in FIG. 2 has the wider second cavity 28 and second gate hole 25a, and thus can be more easily manufactured.
However, in the conventional FEDs shown in FIGS. 1 and 2, short circuit often occurs between the first gate layers 13 and 23 and the field emitters 19 and 29 and between the first gate layers 13 and 23 and the second gate layers 15 and 25. This is because the first gate layers 13 and 23 to which comparatively high voltages are applied are exposed outside of the insulating layers 12, 14, 22, and 24 and intervals between the first gate layers 13 and 23, the field emitters 19 and 29, and the second gate layers 15 and 25 are narrow. In this case, the danger of line breakage on a screen occurs, and the FED and a driving circuit are damaged by overcurrent caused by short circuit, and thus their life spans are shortened.
FIG. 3 illustrates the result of simulation performed on electron beam emission in the conventional FED having the structure shown in FIG. 1. In this simulation, a voltage of 30V is applied to the first gate layer 13, and a voltage of 10V is applied to the second gate layer 15. In FIG. 3, a portion of a strong electric field is marked by a red color.
Referring to FIG. 3, in the prior art, the first gate layer 13 is exposed outside of the insulating layers 12 and 14, and thus, a very strong electric field is focused on an exposed portion of the first gate layer 13. In this case, short circuit may easily occur between the field emitter 19 and the first gate layer 13. In addition, electrons emitted from the field emitter 19 are collided with the exposed portion of the first gate layer 13. As a result, the portion is damaged, and the stability of the FED is lowered.